This invention relates to memory systems and particularly to error correction in such systems and includes both method and apparatus inventions.
The reliability of information read from a memory can be increased by the use of error detection and correction circuits. One method for error detection and correction is the use of redundant bits in each data word. One commonly used error detection arrangement utilizes one or more parity bits each of which indicates whether there is an even or odd number of ones in the data bits associated with that parity bit.
In general, error correction requires more redundant bits than error detection. For example, while a parity check scheme can detect any single bit error it is not capable of error correction in the general case.
It is an object of this invention to provide an error correction method which will correct memory failures due to a predominant mode of failure; namely, a single bit stuck at one or zero.